library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- This module outputs input + 4
entity four_adder is
generic (N : integer :=32);
port(	data_in  : in  std_logic_vector (N-1 downto 0);
		data_out : out std_logic_vector (N-1 downto 0)
);
end four_adder;

architecture Structural of four_adder is
component RCA is
generic(N : integer := 8);
port(	A_rca	: in   std_logic_vector (N-1 downto 0);
		B_rca	: in   std_logic_vector (N-1 downto 0);
		S_rca	: out std_logic_vector (N-1 downto 0);
		C_i		: in   std_logic;
		C_o		: out std_logic
);
end component;
signal four : std_logic_vector(N-1 downto 0);
begin

four(N-1 downto 3) <= (others => '0');
four(2 downto 0) <= "100";

SUM4: RCA generic map (N) port
map (	A_rca	=> data_in,
		B_rca	=> four,
		S_rca	=> data_out,
		C_i		=> '0',
		C_o		=> open
	);
	
end Structural;

